1. Field of the Invention
The invention relates generally to integrated circuits particularly with respect to Superconductive Tunnel junction integrated circuits. The invention will be described particularly with respect to Josephson circuits.
2. Description of the Prior Art
A primary factor determining the efficacy of integrated circuit processes and the concomitant yield thereof is the number of steps comprising the process. For example, if a process consists of twelve steps and the expected yield of each of the steps is seventy-five percent, then the yield of operative devices at the completion of the twelve step process is 0.75.sup.12, or approximately three percent. Generally, this yield is considered unacceptably low. If, however, the process consists of eight steps, each with a yield probability of seventy-five percent, then the final yield for the eight step process is 0.75.sup.8, or ten percent. Thus by eliminating four steps, a three-fold improvement in yield is achieved without any improvement in the quality of the processing. Additionally, large numbers of processing steps engender problems with adhesion, step coverage and damage to prior deposited layers. The longer the fabrication sequence, the lower is the device throughput of the process.
The current state of the art of Josephson junction integrated circuit fabrication is discussed in an article by J. H. Greiner et al entitled "Fabrication Process for Josephson Integrated Circuits", published in the March, 1980 issue of the IBM Journal of Research and Development, Volume 24, No. 2, on page 195 (Reference 1) and in an article by T. R. Gheewala entitled "Design of 2.5-Micrometer Josephson Current Injection Logic (CIL)", published in the March, 1980 issue of the IBM Journal of Research and Development, Volume 24, No. 2 on page 130 (Reference 2). Said References 1 and 2 are incorporated herein by reference. As discussed in said Reference 1, the state of the art of Josephson junction logic integrated circuit fabrication involves approximately 12 deposition steps, 12 photoresist steps, an anodization step and a junction barrier formation step. Table 1 on page 197 of said Reference 1 enumerates the steps for a particular process utilized to fabricate interferometers combined with current injection logic gates. Typically the process comprises depositing four superconducting layers, viz., the ground plane, the lower Josephson electrode, the Josephson counter electrode and the control lines. Interconnections, interferometer loops and other circuit elements are formed from the last three layers. Each superconductive layer is separated from an adjacent superconductive layer by an insulator layer that is patterned to form vias which provide required electrical connections between layers. The deposition of resistors, additional insulator layers for increased inductance, passivation layers and anodization are steps utilized to complete the circuit. Thus it is appreciated that a minimum of nine separate thin films and patterning steps are required in this process. In the fabrication procedure depicted by Table 1 on page 197 of said Reference 1, fifteen layers are utilized. In the art of semiconductor integrated circuit fabrication, there are considered excessive numbers of steps resulting in unacceptably low yields of functional circuits and inordinately long times for circuit fabrication completion.
There are two basic types of Josephson logic gates, viz., current injection gates and magnetically controlled gates. All present day Josephson integrated circuits utilize one or both of these gate types. The fastest logic gates utilize a combination of the two as described in said Reference 2. All of these types of Josephson integrated circuits are subject to the disadvantages described above.